Many complex electronic systems rely on synchronous or clocked digital circuits. For example, a microprocessor or central processing unit (CPU) often has a clock input that controls the timing of operations such as instruction decode and memory access. To ensure reliable operation, the microprocessor may have very strict input requirements for this clock input, such as frequency, voltage levels, and duty cycle.
As system designers compete with one another for the fastest-performing chips, they often squeeze internal delays and resort to design tricks that use both rising and falling edges of the clock. The clock's duty cycle then becomes more critical, since variations in duty cycle reduce available setup times to either the rising or falling edges of the clock. Thus a tendency for tighter duty-cycle requirements has occurred in highly competitive markets.
Clocks are generally produced by a crystal oscillator and passed through a driver before being input to a microprocessor or other very-large-scale-integration (VLSI) chip. System designers can use special clock drivers that adjust the clock's characteristics.
Many duty-cycle correctors use threshold-level compensation. The threshold level is adjusted to adjust the duty cycle. See U.S. Pat. No. 4,959,557 by Miller which uses a feedback loop to adjust the threshold of the input to buffer 48. These threshold-adjustment correctors are limited since adjusting the threshold voltage provides only a small change in duty cycle when a clock with sharp edges (high slew rate) is used. Large duty cycle adjustments, such as from 80%-20% to 50%--50% are not feasible unless perhaps a very slow-slewing clock is used.
Other clock drivers use slew-time compensation to adjust duty cycle over a wide range. A slow-slewing clock signal is modulated in a modulator. The modulator is a complementary metal-oxide-semiconductor (CMOS) inverter with additional transistors in series to power and ground. The additional series transistors have gates connected to a control voltage of about Vcc/2. The control voltage is adjusted slightly to limit current through the series transistors, adjusting a ratio of up and down source currents. This changes the up and down slew rates of the clock. The slow-slewing clock output by the modulator is then cleaned up to a high-slew-rate clock by a driver stage.
For example, U.S. Pat. No. 5,477,180 by Chen uses a CMOS modulator 16 that adjusts up and down source currents. A feedback loop from the modulator output is used to generate a control or bias voltage that controls the up and down source currents in the modulator. While such a circuit is useful, mismatch of R.sub.3 and R.sub.4 resistor values in the feedback loop can introduce duty-cycle detector sensing error. Further inaccuracies may occur since the modulator outputs a slow-slew clock that may need a further driver stage to sharpen the edges to a higher slew rate.
Since Chen's feedback loop senses the output from the modulator rather than the output from a later driver stage, the slow-slew clock is sensed by the feedback loop. Sensing a slow-slew clock rather than a high-slew clock is undesirable since errors can be increased and clock stability diminished. A more linear and stable duty-cycle corrector is desired.
Another duty-cycle adjustor is described in U.S. Pat. No. 5,907,254 by Chang. Two differential amps are used in his feedback loop(s). Both threshold and slew-time compensation are used in this complex feedback. While useful, a more accurate and linear duty-cycle correction circuit is desired that uses a single feedback loop. It is desired that the feedback loop senses the duty cycle of the actual clock driven to the microprocessor, not the slow-slew-rate clock output from the modulator. More accurate filtering of the duty cycle is desired that does not introduce distortions due to resistor mismatch within the filter. A smoothed control voltage is desired for controlling the source currents in the modulator to further reduce distortions and ensure clock stability.